The performance, density, and cost of integrated circuit (IC) chips have been improving at a dramatic rate. Much of the improvement has been due to the ability to scale transistors to increasingly smaller dimensions, resulting in higher speed and higher functional density. The continued shrinking of transistor sizes on the IC chips, however, poses many challenges to back-end interconnects. As the minimum feature size on the IC's shrinks below 0.18 μm, the metal interconnect lines become thinner and more densely packed, resulting in greater resistance in the metal lines and larger inter-metal capacitance, and therefore a longer time delay or slower operating speed. By changing to different materials, i.e., higher conductivity material for the metal lines and lower permittivity (low-k) dielectric for the insulating material, device geometry can continue to shrink without adversely impacting the maximum operating speed. This prompted the switch from aluminum and silicon dioxide to copper and low-k dielectrics in the backend process flow for manufacturing many current and future IC devices.
The switch from aluminum/oxide to copper/low-k involves a variety of fundamental changes in the backend manufacturing process flow. Since it is difficult to etch copper, new approaches such as “damascene” or “dual damascene” processing are required. Copper damascene/dual-damascene is a process where VIAs and/or trenches are etched into the insulating material. Copper is then filled into the VIAs and/or trenches and sanded back using a process such as chemical mechanical polishing (CMP), so the conducting materials are only left in the VIAs and trenches. In the dual damascene approach, both VIAs and trenches are patterned into a layer of dielectric material or a stack of different dielectric materials before copper fill. An advantage of this approach is that only one copper fill and CMP is necessary to form a layer of metal lines and VIAs that connect the layer of metal lines to another layer of metal lines. The dual damascene approach, however, may require a rather complex dielectric stack that includes a sequence of hard mask, low-k dielectrics, and etch stop layers.
Different processing sequences of etching VIAs and trenches in dielectric material(s) can be used in a dual damascene process. FIGS. 1A-1E illustrates a “VIA-first” processing sequence for etching VIAs and trenches in a dielectric stack 120. As shown in FIG. 1A, dielectric stack 120 comprises from top to bottom an optional hard mask layer 122, a first dielectric layer 124, an optional middle stop layer 126, a second dielectric layer 128, and a bottom stop layer 130. The first and second dielectric layers are typically made of a low-k dielectric material. The hard mask layer, the middle stop layer and the bottom stop layer are typically made of silicon oxy-nitride (SiON), tetra-ethyl-ortho-silicate (TEOS) based oxide, silicon carbide, or the like. Dielectric stack 120 is formed on a substrate 150. A first layer of metal lines 140 also formed on substrate 150 lie under the dielectric stack 120.
In the VIA-first sequence shown in FIGS. 1A-1E, a VIA lithography process is performed first (FIG. 1A), which forms a first photoresist mask 110 on top of the dielectric stack 120 to define VIA openings, such as opening 101, for etching VIAs. Then VIAs are etched through dielectric stack 120, stopping at the bottom stop layer 130. After the VIA mask 110 is stripped (FIG. 1B), a trench lithography process is performed (FIG. 1C), which forms a second photoresist mask 112 on top of the dielectric stack 120 to define trench openings, such as opening 102, for etching trenches. As shown in FIG. 1D, the trenches are etched through the hard mask layer 122 and the first dielectric layer 124, stopping at the middle stop layer 126, if such layer is provided. An opening is also etched in bottom stop layer 130. After the trench mask 112 is stripped (FIG. 1D), both the trench and the VIA are filled with copper and the copper fill is planarized with a CMP step (FIG. 1E), resulting in the formation of a second layer of metal lines 142 and connections 144 between the first and second layers of metal lines.
Besides the complex dielectric stack, the dual damascene approach also raises issues with the trench lithography process. After etching the VIAs in the dielectric stack 120, the use of a single layer of photoresist mask 112 on the resulting topography typically results in severe critical dimension (CD) variations. The CD variations are due partly to local reflectivity changes over the substrate, and partly to photoresist thickness variations, both resulting from changes in VIA density across the substrate. One solution to this problem is to use an organic bottom anti-reflective coating (BARC). As shown in FIG. 2A, a BARC layer 115 can be spin-applied to fill the VIAs and cover the dielectric stack before trench lithography. The BARC helps to make the reflectivity more uniform, and to decrease variations in surface topography resulting from the presence of VIAs. A BARC etching process is usually performed to clear away the BARC 315 in trench openings (i.e., portions of the BARC 315 not covered by the trench mask 112) before etching the trenches.
The spin-applied BARC, however, typically does not fill a dense array of VIAs and isolated VIAs in the same way. Usually, isolated VIAs are filled more easily than dense VIAs, resulting in large variation of BARC thickness on top of the dielectric stack between dense and isolated VIA structures. The non-uniform BARC thickness raises several issues. Firstly, because etch rates of typical organic BARCs are similar to that of the photoresist, a thick photoresist mask is usually required so that, after the BARC at all trench openings is etched away, enough photoresist mask is left for the subsequent trench etching process. The requirement of the thick photoresist mask is disadvantageous for CD control, especially when small dimensions are involved. Secondly, while the BARC at the trench openings is being cleared, portions of hard mask layer 122 in dielectric stack 120 are exposed to the BARC etching process at different times, resulting in the part of the hard mask over dense VIAs being etched more than the part of the hard mask over isolated VIAs. The non-uniform thickness of the hard mask leads to non-uniform trench depth during the subsequent trench etching process, so that the middle stop layer 126 becomes necessary for trench depth uniformity control.
The BARC fill and the trenching etching process may also lead to other problems, such as fencing and facet formation in the trenches, as shown in FIGS. 2B and 2C, which may cause degradation of the IC devices being fabricated.